1. Field of the Invention
Generally, the present disclosure relates to microstructures, such as advanced integrated circuits, and, more particularly, to conductive structures, such as copper-based metallization layers, comprising wide metal lines connected to closely spaced narrow metal lines by transition vias.
2. Description of the Related Art
In the fabrication of modern microstructures, such as integrated circuits, there is a continuous drive to steadily reduce the feature sizes of microstructure elements, thereby enhancing the functionality of these structures. For instance, in modern integrated circuits, minimum feature sizes, such as the channel length of field effect transistors, have reached the deep sub-micron range, thereby increasing performance of these circuits in terms of speed and/or power consumption and/or diversity of functions. As the size of individual circuit elements is reduced with every new circuit generation, thereby improving, for example, the switching speed of the transistor elements, the available floor space for interconnect lines electrically connecting the individual circuit elements is also decreased. Consequently, the dimensions of these interconnect lines are also reduced to compensate for a reduced amount of available floor space and for an increased number of circuit elements provided per unit die area as typically the number of interconnections required increases more rapidly than the number of circuit elements. Thus, a plurality of stacked “wiring” layers, also referred to as metallization layers, is usually provided, wherein individual metal lines of one metallization layer are connected to individual metal lines of an overlying or underlying metallization layer by so-called vias. Despite the provision of a plurality of metallization layers, reduced dimensions of the interconnect lines are necessary to comply with the enormous complexity of, for instance, modern CPUs, memory chips, ASICs (application specific ICs) and the like.
Advanced integrated circuits, including transistor elements having a critical dimension of 0.05 μm and even less, may, therefore, typically be operated at significantly increased current densities of up to several kA per cm2 in the individual interconnect structures, despite the provision of a relatively large number of metallization layers, owing to the significant number of circuit elements per unit area. Consequently, well-established materials, such as aluminum, are being replaced by copper and copper alloys, a material with significantly lower electrical resistivity and improved resistance to electromigration even at considerably higher current densities compared to aluminum. The introduction of copper into the fabrication of microstructures and integrated circuits comes along with a plurality of severe problems residing in copper's characteristic to readily diffuse in silicon dioxide and a plurality of low-k dielectric materials, which are typically used in combination with copper in order to reduce the parasitic capacitance within complex metallization layers. In order to provide the necessary adhesion and to avoid the undesired diffusion of copper atoms into sensitive device regions, it is, therefore, usually necessary to provide a barrier layer between the copper and the dielectric material in which the copper-based interconnect structures are embedded. Although silicon nitride is a dielectric material that effectively prevents the diffusion of copper atoms, selecting silicon nitride as an interlayer dielectric material is less than desirable, since silicon nitride exhibits a moderately high permittivity, thereby increasing the parasitic capacitance of neighboring copper lines, which may result in non-tolerable signal propagation delays. Hence, a thin conductive barrier layer that also imparts the required mechanical stability to the copper is usually formed to separate the bulk copper from the surrounding dielectric material, thereby reducing copper diffusion into the dielectric materials and also reducing the diffusion of unwanted species, such as oxygen, fluorine and the like, into the copper. Furthermore, the conductive barrier layers may also provide highly stable interfaces with the copper, thereby reducing the probability for significant material transport at the interface, which is typically a critical region in view of increased diffusion paths that may facilitate current-induced material diffusion. Currently, tantalum, titanium, tungsten and their compounds with nitrogen and silicon and the like are preferred candidates for a conductive barrier layer, wherein the barrier layer may comprise two or more sub-layers of different composition so as to meet the requirements in terms of diffusion suppressing and adhesion properties.
Another characteristic of copper significantly distinguishing it from aluminum is the fact that copper may not be readily deposited in larger amounts by chemical and physical vapor deposition techniques, thereby requiring a process strategy that is commonly referred to as the damascene or inlaid technique. In the damascene process, first, a dielectric layer is formed, which is then patterned to include trenches and/or vias which are subsequently filled with copper, wherein, as previously noted, prior to filling in the copper, a conductive barrier layer is formed on sidewalls of the trenches and vias. The deposition of the bulk copper material into the trenches and vias is usually accomplished by wet chemical deposition processes, such as electroplating and electroless plating, thereby requiring the reliable filling of vias with an aspect ratio of 5 and more with a diameter of 0.3 μm or even less in combination with trenches having a width ranging from 0.1 μm to several μm. Electrochemical deposition processes for copper are well established in the field of electronic circuit board fabrication. However, for the dimensions of the metal regions in semiconductor devices, the void-free filling of high aspect ratio vias is an extremely complex and challenging task, wherein the characteristics of the finally obtained copper-based interconnect structure significantly depend on process parameters, materials and geometry of the structure of interest. Since the basic geometry of interconnect structures is substantially determined by the design requirements and may, therefore, not be significantly altered for a given microstructure, it is of great importance to estimate and control the impact of materials, such as conductive and non-conductive barrier layers, of the copper microstructure and their mutual interaction on the characteristics of the interconnect structure to insure both high yield and the required product reliability.
In addition to achieve high production yield and superior reliability of the metallization system, it is also important to achieve production yield and reliability on the basis of a high overall throughput of the manufacturing process under consideration. For instance, the so-called dual damascene process is frequently used, in which a via opening and a corresponding trench are filled in a common deposition sequence, thereby providing superior process efficiency. Due to a complex layout of sophisticated metallization systems, the metal lines of two adjacent metallization layers may have a very different lateral size, since metal lines of one layer may have to be adapted to a moderately high packing density of corresponding interconnect structures, while the trenches in the adjacent metallization layer may have to provide a high current drive capability. In this case, the vertical interconnection between a metal line with an increased width to a metal line having a significantly smaller width may have to be established on the basis of a via that corresponds to the trench having the significantly reduced width. A manufacturing regime according to the dual damascene strategy may, however, result in significant irregularities during the deposition of the copper material due to the significant difference in their lateral width of the corresponding trench and the via, as will be explained in more detail with reference to FIGS. 1a-1b. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 at a manufacturing stage in which a complex metallization system 130 is to be formed above a substrate 101. It should be appreciated that the substrate 101 may comprise a plurality of circuit elements, such as transistors and the like, which may be formed on the basis of design dimensions of approximately 50 nm and less, if sophisticated applications are considered. For convenience, any such circuit elements are not shown in FIG. 1a. The metallization system 130 comprises a metallization layer 110, which may represent any of a plurality of metallization layers, wherein the number of corresponding metallization layers may depend on the complexity of the circuit layout of the device 100. For instance, the metallization layer 110 comprises a dielectric material 111, which may include a low-k dielectric material in order to reduce the parasitic capacitance between adjacent metal lines 112, which, at least in the portion shown in FIG. 1a, may represent closely spaced metal lines as may be required by the overall circuit layout. For instance, the metal lines 112 may have a width 112W of approximately 100 nm and less, and the distance between an adjacent two of the metal lines 112 may be of a similar order of magnitude. As previously discussed, the metal lines may be formed on the basis of a copper material in combination with a conductive barrier material 112B in order to provide the required copper confinement and the electromigration behavior, as discussed above. Furthermore, an dielectric cap or etch stop layer 113 is typically provided on the dielectric material 111 and the metal lines 112, wherein the cap layer 113 may, depending on the overall process strategy, also provide copper confinement and superior interface characteristics with the metal lines 112. Furthermore, a metallization layer 120 is formed above the layer 110 and comprises a trench 121T and a via opening 121V formed in a corresponding dielectric material 121. For example, the dielectric material 121 may represent a low-k dielectric material or any other dielectric material, depending on requirements with respect to parasitic capacitance and the like. The trench 121T may have a significantly greater width 121W in order to provide sufficient current drive capability, which may be required in the metallization layer 120. On the other hand, the via opening 121V may connect to one of the metal lines 112 so that a corresponding width 121U substantially corresponds to the width 112W of the metal lines 112 in the metallization layer 110.
The semiconductor device 100 as illustrated in FIG. 1a may be formed on the basis of well-established manufacturing techniques. For example, after providing any circuit elements in the device level of the device 100 (not shown), an appropriate contact structure may be provided to connect to the circuit elements and provide a platform for forming thereon the metallization system 130. Thereafter, one or more metallization layers may be formed on the basis of process techniques as will be described with reference to the metallization layer 120. Thus, after forming the metallization layer 110 and depositing the cap layer 113 on the basis of well-established deposition techniques, such as chemical vapor deposition (CVD) and the like, in order to provide one or more materials, such as silicon carbide, nitrogen-containing silicon carbide and the like, the dielectric material 121 is deposited. For this purpose, any appropriate deposition technique may be used, depending on the composition of the material 121. Thereafter, various process strategies are typically used in order to form the via opening 121U and the trench 121T according to the design dimensions. For example, in a so-called “via first-trench last” approach, the via opening 121V may be formed by providing an etch mask, such as a resist mask, and etching the dielectric material 121 down to a specified depth or down to the etch stop layer 113. Next, a corresponding etch mask for the trench may be formed on the basis of sophisticated lithography techniques, wherein, if required, a corresponding planarization material may be deposited first in order to at least partially fill the via opening 121V, when extending down to the etch stop layer 113. Thereafter, a further etch process is performed to obtain the trench 121T and the etch mask may be removed, while the etch stop layer 113 is also opened so that the via opening 121V may extend into the metal line 112. Thereafter, any required manufacturing processes may be performed for preparing the device 100 for the deposition of a conductive barrier material.
For example, a barrier material 122B is deposited, for instance, in the form of a tantalum/tantalum nitride layer stack on the basis of sputter deposition and the like. Moreover, a seed material (not shown) may be deposited in order to enhance a subsequent electrochemical deposition process for filling in the copper material into the trench 121T and the via 121V. It should be appreciated that, due to the sophisticated device geometries caused by the wide trench 121T and the narrow via 121V, corresponding deposition parameters may have to be appropriately selected in order to reliably cover the exposed portions within the trench 121T and the via 121V with the barrier material 122B.
FIG. 1b schematically illustrates the semiconductor device 100 when subjected to an electrochemical deposition process for depositing copper material. As previously explained, in view of superior process efficiency, the trench 121T and the via 121V may be formed in an interrelated patterning process and the filling thereof may be accomplished on the basis of the common deposition process 102. However, the sophisticated device topography caused by the per se very complex electrochemical deposition of the copper material may result in deposition irregularities, such as voids 122C, thereby contributing to significant yield losses and reduced reliability of the resulting metallization system 130. That is, the electrochemical deposition of the copper material 122A may be based on highly complex electrolyte solutions including sophisticated additives in order to obtain, in combination with an appropriate pulse reverse regime in electroplating techniques, a bottom to top fill behavior. However, due to the significant difference in lateral dimensions of the trench 121T and the via 121V, a premature “closure” of the via opening 121V may result in a corresponding irregularity 122C.
In some conventional strategies, the probability of creating the deposition-related irregularities 122C may be reduced by redesigning the layout of the metallization layer 110 so that increased areas are provided at certain portions of the metal lines 112 so as to provide an increased lateral size of the “landing area” of the via 121V. However, a corresponding redesign may generally reduce overall packing density in the metallization system 130.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.